1. Technical Field of the Invention
The present invention relates to an architecture for implementing an integrated capacitance.
The invention particularly, but not exclusively, relates to an architecture for implementing an integrated capacity to be used as tank capacitor in a converter of the Voltage Down type and the following description is made with reference to this field of application by way of illustration only.
2. Description of Related Art
Different architectures for converters of the voltage down type are known in the literature and are widely used.
In particular, in the field of Flash memories, it is known to use converters of the voltage down type or VDC converters (acronym for “Voltage Down Converter”) to allow the use of transistors with gate oxides having thickness lower than 40 Å (Angstrom) in applications requiring conventional supply voltage values, in particular equal to 3V.
In this case, a VDC converter of the known type allows one to obtain a regulated voltage with values equal or lower than 1.8V starting from an external supply voltage in the range 2.4-4.0V. It is also possible, by using a booster circuit inserted in the VDC converter, to obtain a correct regulation also with an external supply voltage with values up to 2V.
In particular, known VDC converters essentially comprise an open or closed loop regulation circuit connected to an output driver, realized for example by means of a MOS transistor with N channel or P channel.
In the case of application to a Flash memory of the NOR type, characterized by extremely quick impulsive consumption (from 0 to tens of mA in less than 10 ns) due to the reading architecture of the asynchronous type with response times in the order of 50 ns, it is also known to use a channel width modulation VDC converter, schematically shown in FIG. 1 and globally indicated with reference 1.
The channel modulation VDC converter 1 essentially comprises a regulator 2 of the closed loop series type connected to an output driver 3, in particular realized by means of a Mout transistor of the NMOS type.
The regulator 2 has the task of generating a reference voltage signal VREF having a value equal to a voltage value which is to be present at the output.
In particular, the regulator 2 comprises an operational amplifier A supplied by a first voltage reference, in particular a supply voltage reference Vdd and having a first input terminal connected to an input terminal IN of the channel modulation VDC converter 1, a second input terminal connected, by means of a first impedance element Z1, to a second voltage reference, in particular a ground reference GND, as well as an output terminal connected to a control terminal of the transistor Mout of the output driver 3.
The input terminal IN of the channel modulation converter VDC 1 supplies to the first input terminal of the operational amplifier A of the regulator 2 a stable voltage signal VBGAP.
It is also possible to use, as supply voltage reference of the operational amplifier A, a boosted voltage reference Surv.
The regulator 2 also comprises a second impedance element Z2 connected between the second input terminal of the operational amplifier A and a first conduction terminal of the transistor Mout of the output driver 3, having in turn a second conduction terminal connected to the supply voltage reference Vdd and the control terminal connected to a terminal O3 of the output driver 3.
The channel modulation converter VDC 1 also comprises a stand by driver 4, in particular realized by means of a transistor Msb of the NMOS type inserted between a first voltage reference, in particular a supply voltage reference Vdd and an output terminal OUT of the channel modulation VDC converter 1 and having a control terminal connected to the output terminal O3 of the output driver 3.
Moreover, the channel modulation converter VDC 1 comprises a power block 5, inserted between the supply voltage reference Vdd and the output terminal OUT of the channel modulation converter VDC 1 and realized by means of a plurality of transistors M1 . . . MN, in particular transistors of the NMOS type, inserted, in parallel to each other, between the supply voltage reference Vdd and the output terminal OUT and having the control terminals connected to each other and to the control terminal of the transistor Msb of the stand by driver 4.
In particular, the transistors M1 . . . MN of the power block 5 are connected to the supply voltage reference Vdd by means of a plurality of switches SW1 . . . SWN subjected to a plurality of control signals S1 . . . SN generated by a control block 6, in turn being input an output voltage signal VOUT on the output terminal OUT of the channel modulation converter VDC 1 and the voltage reference signal VREF generated by the regulator 2.
In this way, the power block 5 is able to supply a current value requested by a load connected to the channel modulation converter VDC 1 by means of turning on the transistors M1 . . . MN. In particular, the control block 6 compares the value of the reference voltage signal VREF with the value of the output voltage signal VOUT and drives, by means of the control signals S1 . . . SN the partial or total turn on and off of the transistors M1 . . . MN, which can thus be considered output drivers.
In this way, the channel modulation converter VDC 1 allows to adapt, quickly enough, the transconductance value of the output driver 3 on the basis of the current requests of a load associated with the converter itself. In particular, the power block 5 allows to control this transconductance value through a dynamic modulation of the channel width W thanks to the activation/deactivation of the transistors M1 . . . MN in parallel to each other, thus obtaining a regulated output voltage signal VOUT.
Moreover, the stand by driver 4 realizes an open loop replication of the reference voltage signal VREF, for supplying a weak current value requested in the stand-by mode, thus allowing the turn off of the power block 5 to limit the overall consumption of the channel modulation converter VDC 1 in this mode.
The channel modulation converter VDC 1 finally comprises a so called tank capacitor CTANK inserted between its output terminal OUT and the ground reference GND.
This tank capacitor CTANK allows to sustain the output voltage signal VOUT in the brief transient necessary for the channel modulation converter VDC 1 to reach an activation state of the regulation. In other words, the role of the tank capacitor CTANK is that of addressing currents of the impulse type dissipated by a load connected to the channel modulation converter VDC 1 and thus avoid a temporary “breakdown” of the regulated output voltage signal VOUT.
To do this it is possible to use a capacitor having a value equal to only 2 nF, making the channel modulation converter VDC 1 compatible with an integrated solution.
In reality, in sub-micrometric technologies with oxide thickness in the order of 40 Angstrom, to avoid relatively low performances due to the faultiness of the oxide layers, this tank capacitor CTANK is to be realized through the series of two capacitors of double value, as shown in FIG. 2.
It is to be remembered in fact that, in general, using a series of capacitors is very expensive in terms of area occupation on the silicon and thus unadvised in integrated applications. In the case at issue, having to use capacitors with high value (in the order of nano-farads), and to avoid having to “eliminate” a device which, in the testing step, has a fault on these capacitors the series of two capacitors is used so that, if one of these capacitors has a “leakage” current the presence of the other capacitor allows to ensure the regular operation, the possibility that both the capacitors have leakage currents being very low.
This solution however implies a great waste of integration area on silicon and thus makes the channel modulation converter VDC 1 less attractive for integrated applications in these technologies.
There is accordingly a need for providing an integrated capacitor, in particular to be used as tank capacitor in a channel modulation converter VDC, having reduced integration area occupation on silicon so as to allow to overcome the limits and the drawbacks still affecting the solutions used by the prior art.